Controller area network (bxCAN)
RM0008
Filter bank i register x (CAN_FiRx) (i=0..27 in connectivity line devices,, x=1,
2)
Address offsets: 0x240..0x31C
Reset value: undefined
Note:
In connectivity line devices there are 28 filter banks, i=0 .. 27, in other devices there are 14
filter banks i = 0 ..13. Each filter bank i is composed of two 32-bit registers, CAN_FiR[2:1].
This register can only be modified when the FACTx bit of the CAN_FAxR register is cleared
or when the FINIT bit of the CAN_FMR register is set.
31
FB31
rw
15
FB15
rw
30
FB30
rw
14
FB14
rw
29
FB29
rw
13
FB13
rw
28
FB28
rw
12
FB12
rw
27
FB27
rw
11
FB11
rw
26
FB26
rw
10
FB10
rw
25
FB25
rw
9
FB9
rw
24
FB24
rw
8
FB8
rw
23
FB23
rw
7
FB7
rw
22
FB22
rw
6
FB6
rw
21
FB21
rw
5
FB5
rw
20
FB20
rw
4
FB4
rw
19
FB19
rw
3
FB3
rw
18
FB18
rw
2
FB2
rw
17
FB17
rw
1
FB1
rw
16
FB16
rw
0
FB0
rw
In all configurations:
Bits 31:0 FB[31:0] : Filter bits
Identifier
Each bit of the register specifies the level of the corresponding bit of the expected identifier.
0: Dominant bit is expected
1: Recessive bit is expected
Mask
Each bit of the register specifies whether the bit of the associated identifier register must
match with the corresponding bit of the expected identifier or not.
0: Don’t care, the bit is not used for the comparison
1: Must match, the bit of the incoming identifier must have the same level has specified in
the corresponding identifier register of the filter.
Note:
582/995
Depending on the scale and mode configuration of the filter the function of each register can
differ. For the filter mapping, functions description and mask registers association, refer to
A Mask/Identifier register in mask mode has the same bit mapping as in identifier list
mode.
For the register mapping/addresses of the filter banks please refer to the Table 164 on
Doc ID 13902 Rev 9
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